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CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
September 2004
CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
General Description
The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the CLC031A include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. The unique multi-functional I/O port of the CLC031A provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the CLC031A to the desired application. The CLC031A is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance. The CLC031A has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port. The CLC030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the CLC031A. The CLC031A's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.
Features
n SDTV/HDTV serial digital video standard compliant n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps serial video data rates with auto-detection n LSB de-dithering option n Uses low-cost 27MHz crystal or clock oscillator reference n Fast VCO lock time: < 500 s at 1.485 Gbps n Built-in self-test (BIST) and video test pattern generator (TPG)* n Automatic EDH/CRC word and flag processing n Ancillary Data FIFO with extensive packet handling options n Adjustable, 4-deep parallel output video data FIFO n Flexible control and configuration I/O port n LVCMOS compatible control inputs and clock and data outputs n LVDS and ECL-compatible, differential, serial inputs n 3.3V I/O power supply and 2.5V logic power supply operation n Low power: typically 850mW n 64-pin TQFP package n Commercial temperature range 0C to +70C * Patent applications made or pending.
Applications
n SDTV/HDTV serial-to-parallel digital video interfaces for: -- Video editing equipment -- VTRs -- Standards converters -- Digital video routers and switchers -- Digital video processing and editing equipment -- Video test pattern generators and digital video test equipment -- Video signal generators
Ordering Information
Order Number CLC031AVEC Package Type 64-Pin TQFP NS Package Number VEC-64A
(c) 2004 National Semiconductor Corporation
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Typical Application
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Block Diagram
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Connection Diagram
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64-Pin TQFP Order Number CLC031AVEC See NS Package Number VEC-64A
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Absolute Maximum Ratings (Note 1)
It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. CMOS I/O Supply Voltage (VDDIO-VSSIO): SDI Supply Voltage (VDDSI-VSSSI): Digital Logic Supply Voltage (VDDD-VSSD): PLL Supply Voltage (VDDPLL-VSSPLL): CMOS Input Voltage (Vi): CMOS Output Voltage (Vo): 4.0V 4.0V 3.0V 3.0V VSSIO -0.15V to VDDIO +0.15V VSSIO -0.15V to VDDIO +0.15V
CMOS Input Current (single input): Vi = VSSIO -0.15V: Vi = VDDIO +0.15V: CMOS Output Source/Sink Current: IBB Output Current: IREF Output Current: SDI Input Voltage (Vi): Package Thermal Resistance JA @ 0 LFM Airflow JA @ 500 LFM Airflow JC Storage Temp. Range: Junction Temperature: Lead Temperature (Soldering 4 Sec): ESD Rating (HBM): ESD Rating (MM): 40.1C/W 24.5C/W 5.23C/W -65C to +150C +150C +260C 6.0 kV 400 V -5 mA +5 mA
6 mA
+300 A +300 A VSSSI -0.15V to VDDSI +0.15V
Recommended Operating Conditions
Symbol VDDIO VDDSD VDDD VDDPLL TA Parameter CMOS I/O Supply Voltage SDI Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage Operating Free Air Temperature Conditions VDDIO-VSSIO VDDSI-VSSSI VDDD-VSSD VDDPLL-VSSPLL 0 +70 C Reference Min 3.150 Typ 3.300 Max 3.450 Units V
2.375
2.500
2.625
V
Required Input Conditions
(Note 9) Symbol VIN t r , tf Parameter Input Voltage Range Rise Time, Fall Time 10%-90% SMPTE 259M, Level C SMPTE 259M, Level D BRSDI Serial Input Data Rate SMPTE 344M SMPTE 292M SMPTE 292M VCM(SDI) VIN(SDI) VIN(SDI) Common Mode Voltage SDI Serial Input Voltage, Single-ended SDI Serial Input Voltage, Differential 20%-80%, SMPTE 259M Data Rates 20%-80%, SMPTE 292M Data Rates SDI, SDI VIN = 125 mVP-P VSSSI +1.0V 125 125 0.4 800 800 1.0 SDI, SDI Conditions Reference All LVCMOS Inputs Min VSSIO 1.0 1.5 270 360 540 1,483 1,485 VDDSI -0.05V 880 880 1.5 270 V mVP-P mVP-P ns ps MBPS Typ Max VDDIO 3.0 Units V ns
t r , tf
Rise Time, Fall Time
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Required Input Conditions
Symbol fACLK DCACLK t r , tf Parameter Ancillary / Control Data Clock Frequency Duty Cycle, Ancillary Clock Ancillary / Control Clock and Data Rise Time, Fall Time Setup Time, ADN to ACLK or ION to ACLK Rising Edge Hold Time, Rising Edge ACLK to ADN or ACLK to ION Bias Supply Reference Resistor External Clock Frequency Crystal Frequency
(Continued) Conditions Reference Min Typ Max VCLK ACLK 45 1.0 50 1.5 55 3.0 Units MHz % ns
10%-90%
tS
3.0 Control Data Input or I/O Bus Input ION, ADN, ACLK Timing Diagram 3.0
1.5
ns
tH
1.5
ns
RREF fEXT CLK fXTAL
Tolerance 1% Ext Clk Figure 6 XTALo, XTALi -100 ppm
4.75k 27.0 +100 ppm
MHz
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol VIH VIL IIH IIL VOH VOL VOHV VOLP VSDI ISDI VTH IBB IREF IDD Parameter Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Low Level Minimum Dynamic VOH Maximum Dynamic VOL Serial Data Input Voltage Serial Data Input Current Input Thereshold Bias Supply Output Current Reference Output Current Power Supply Current, (3.3V) 3.3V Supply, Total Power Supply Current, 2.5V Supply, Total Over VCM range RBB = 8.66k 1% RREF = 4.75k 1% 270MBPS Data Rate 1,485MBPS Data Rate 270MBPS Data Rate 1,485MBPS Data Rate VDDIO, VDDSI VDDD, VDDPLL -220 -290 SDI, SDI VIH = VDDIO(Note 8) VIL = VSSIO IOH = -2 mA IOL = +2 mA IOH = -2 mA (Note 6) IOL = +2 mA (Note 6) 125 All LVCMOS Outputs 2.4 VSSIO All LVCMOS Inputs Conditions Reference Min 2.0 VSSIO +85 -1 2.7 VSSIO +0.3 VDDIO -0.5 VSSIO +0.4 800 880 mVP-P A mV A 45.0 50.0 120 340 Typ Max VDDIO 0.8 +150 -20 VDDIO VSSIO +0.5V V Units V A
1
10
< 100
-188 -262 38.0 47.0 80 220
mA mA
IDD (2.5V)
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AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions SMPTE 259M, Level C SMPTE 259M, Level D BRSDI Serial Input Data Rate SMPTE 344M SMPTE 292M SMPTE 292M 20%-80%, SMPTE 259M Data Rates 20%-80%, SMPTE 292M Data Rates SMPTE 259M, 270MBPS fVCLK Video Output Clock Frequency SMPTE 267M, 360MBPS SMPTE 344M, 540MBPS SMPTE 292M, 1,483MBPS SMPTE 292M, 1,485MBPS tpd DCV Propagation Delay, Video Clock to Video Data Valid Duty Cycle, Video Clock 27MHz tJIT Video Data Output Clock Jitter 36MHz 54MHz 74.25MHz Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs fACLK DCA tr, tf tS Ancillary / Control Data Clock Frequency Duty Cycle, Ancillary Data Clock Output Rise Time, Fall Time Setup Time, ADN to ACLK or ION to ACLK Rising Edge Hold Time, Rising Edge ACLK to ADN or ACLK to ION Propagation Delay, Clock to Control Data Propagation Delay, Clock to Ancillary Data ANC Data clock (Note 7) 10%-90% ION, ADN, ACLK Timing Diagram VCLK ACLK 45 1.0 3.0 50 1.5 1.5 55 3.0 % MHz VCLK 50%-50% VCLK to DVN Timing Diagram VCLK VCLK 27.0 36.0 54.0 74.176 74.25 0.5 505 2.0 1.4 1.0 0.5 nsP-P 2.0 ns % MHz SDI, SDI 0.4 Reference Min Typ 270 360 540 1,483 1,485 1.0 1.5 270 pns ps MBPS Max Units Serial Video Data Inputs
t r , tf
Rise Time, Fall Time
Parallel Video Data Outputs
tH
Control Data Input or I/O Bus Input
ns
3.0
1.5
Parallel Ancillary / Control Data Outputs tpd tpd ACLK to ADN Timing Diagram 8.5 ns 11.5
50%-50%
Multi-function Parallel I/O Bus tr, tf Rise Time, Fall Time 10%-90% IO0-IO7 Timing Diagram 1.0 1.5 3.0 ns
PLL/CDR, Format Detect tLOCK tFORMAT Lock Detect Time Format Detect Time SD Rates (Note 5) HD Rates (Note 5) All Rates 0.32 0.26 20 1.0 1.0 ms
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics" specifies acceptable device operating conditions.
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AC Electrical Characteristics
Note 4: Spec. is guaranteed by design.
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Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSSIO = VSSD = VSSSI = 0V. Note 3: Typical values are stated for VDDIO = VDDSI = +3.3V, VDDD = VDDPLL = +2.5V and TA = +25C. Note 5: Measured from rising-edge of first SDI cycle until Lock Detect bit goes high (true). Lock time includes CDR phase acquisition time plus PLL lock time. Note 6: VOHV and VOLP are measured with respect to reference ground. VOLP is the peak output LOW voltage or ground bounce that may occur under dynamic simultaneous output switching conditions. VOHV is the lowest output HIGH voltage or output droop that may occur under dynamic simultaneous output switching conditions. Note 7: When used to clock control data into or from the CLC031A, the duty cycle restriction does not apply. Note 8: IIH includes static current required by input pull-down devices. Note 9: Required Input Conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order for it to produce the specified DC and AC electrical output characteristics. Note 10: Functional and certain other parametric tests utilize a CLC030 as the input source to the SDI inputs of the CLC031A. The CLC030 is DC coupled to the inputs of the CLC031A. Typical VIN = 800 mV, VCM = 2.9 V.
Test Loads
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Test Circuit
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Timing Diagram
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Device Operation
INTRODUCTION The CLC031A SMPTE 292M/259M Digital Video Deserializer/Decoder is used in digital video signal origination and destination equipment: cameras, video tape recorders, telecines, editors, standards converters, video test and other equipment. It decodes and converts serial SDTV or HDTV component digital video signals into parallel format. The CLC031A decoder/deserializer processes serial digital video (SDV) signals conforming to SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M and operates at serial data rates of 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps. Corresponding parallel output data rates are 27.0 MHz, 36.0 MHz, 54.0 MHz, 74.176MHz and 74.25 MHz. The CLC031A accepts ECL or LVDS serial data input signals. Outputs signals are compatible with LVCMOS logic devices. Note: In the following explanations, these logical equivalences are observed: ON Enabled Set True Logic_1 and OFF Disabled Reset False Logic_0.
VIDEO DATA PATH The Serial Data Inputs (SDI) accept serial video data at SMPTE 259M standard definition, SMPTE 344M (proposed) or SMPTE 292M high-definition data rates. These inputs accept standard ECL or LVDS signal levels and may be used single-ended or differentially. Inputs may be DC or AC coupled, as required, to devices and circuits supplying the data. Recommended operating conditions and all input DC and AC voltage and current specifications shall be observed when designing the input coupling circuits. For convenience, a reference bias source, pin name RREF, sets the reference current available from the input bias source, pin name RBB. The recommended nominal value of RREF is 4.75k, 1%. RBB is provided so that the SDI inputs may be supplied DC bias voltage via external resistors when the inputs are AC-coupled. The bias source should be loaded with a resistance to the VSS supply. The source current available at RBB is 200A. Figure 1 shows a typical input biasing scheme using RBB and RREF.
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Device Operation
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clock. Interraction and operation of the character alignment control signals and indicators Framing Mode, Framing Enable and NSP (New Sync Position) is described later in this datasheet. The CLC031A implements TRS character LSB-clipping as prescribed in ITU-R BT.601. LSB-clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done after descrambling and de-dithering. Once the PLL attains lock, the video format detector processes the received data to determine the raster characteristics (video data format) and configure the CLC031A to handle it. This assures that the parallel output data will be properly formatted, that the correct data rate is selected and that Ancillary Data and CRC/EDH data are correctly detected and checked. Supported parallel data formats or subformats may belong to any one of several component standards: SMPTE 125M, SMPTE 267M, SMPTE 260M, 274M, 295M or 296M. Refer to Table 4 for the supported formats. (See also the Section Application Information section for handling of other raster formats or format extensions developed after this device was designed). The detected video standard information is passed to the device control system and saved in the control registers from whence it may be read by the user. The CLC031A may be configured to operate in a single video format by loading the appropriate FORMAT SET[4:0] control data into the FORMAT 0 control register. Also, the CLC031A may be configured to handle only the standard-definition data formats by setting the SD ONLY bit or only the highdefinition data formats by setting the HD ONLY bit in the FORMAT 0 control register. When both bits are reset, the default condition, the part automatically detects the data rate and range. Aligned and de-processed parallel data passes into a variable-depth video FIFO prior to output. Video FIFO depth from 0 to 4 registers is set by a 3-bit word written into the VIDEO FIFO Depth[2:0] bits in the ANC 0 control register. The video FIFO permits adjustment of the parallel video data output timing or delay at a parallel word rate. The occurence of corresponding TRS indicator bits, EAV, SAV and NSP, in the control register corresponds to the input register position of the FIFO. This positioning permits a look-ahead function in which the alignment status of the video data can be determined up to four parallel clock periods prior to the appearance of that data at the parallel data output. The parallel video data is output on DV[19:0]. The 20-bit parallel video data is organized so that for HDTV data, the upper-order 10 bits DV[19:10] are luminance (luma) information and the lower 10 bits DV[9:0] are colour difference (chroma) information. SDTV data use the lower-order 10-bits DV[9:0] for both luma and chroma information. (The SDTV parallel data is also duplicated on DV[19:10]). VCLK is the parallel output word rate clock signal. The frequency of VCLK is appropriate to either the HD or SD data being processed. Data is valid between the falling edges of a VCLK cycle. Data may be clocked into external devices on the rising-edge of VCLK. The DV[19:0] and VCLK signals are LVCMOScompatible.
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FIGURE 1. Optional Input Biasing Scheme The SMPTE descrambler receives NRZI serial data, converts it to NRZ, then decodes it to either 10-bit standard definition or 20-bit high definition parallel video data using the reverse polynomial X9 + X4 + 1 as specified in the respective standard: SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The data reception bit order is LSB-first. All data processing is done at the parallel rate. The CLC031A incorporates circuitry that implements a method for handling data that has been subjected to LSB dithering. When so enabled, data from the de-scrambler is routed for de-dithering. The De-Dither Enable bit in the VIDEO INFO 0 control register enables this function. Dedithering of data present in the vertical blanking interval can be selectively enabled by use of the V De-Dither Enable bit in the VIDEO INFO 0 control register. The initial condition of De-Dither Enable and V De-Dither Enable is OFF. The descrambler supplies signals to theTRS character detector which identifies the presence of the valid video data. The TRS character detector processes the timing reference signals which control raster framing. TRS (sync) characters are detected and the video is aligned on word boundaries. Data is re-synchronized with the parallel word-rate
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CLC031A
Device Operation
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ANCILLARY/CONTROL DATA PATH The 10-bit ancillary and Control Data Port AD[9:0] serves two functions in the CLC031A. Ancillary Data from the Ancillary Data FIFO is output from this port after its recovery from the video data stream. The utilization and flow of Ancillary Data from the device is managed by a system of control bits, masks and IDs stored in the control data registers. This port also provides read/write access to contents of the configuration and control registers. The signals RD/WR, ANC/ CTRL and ACLK control data flow through the port. CONTROL DATA FUNCTIONS Control data is input to and output from the CLC031A using the lower-order 8 bits AD[7:0] of the ancillary/Control Data Port. This control data initializes, monitors and controls operation of the CLC031A. The upper two bits AD[9:8] of the port function as handshaking signals with the device accessing the port. When either a control register read or write address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). When control data is being written to the port, AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]). When control data is being read from the port, the CLC031A will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Note: After either a manual or power-on reset, ACLK must be toggled three (3) times to complete initiallization of the Ancillary and Control Data Port. The sequence of clock and control signals for reading control data from the ancillary/control data port is shown in Figure 2. Control data read mode is invoked by making the ANC/ CTRL input low and the RD/WR input high. The 8-bit address of the control register set to be accessed is input to the port on bits AD[7:0]. To identify the data as an address, AD[9:8] must be driven as 00b. The complete address word will be 0XXh, where 0 is AD[9:8] and XX are AD[7:0]. The address is captured on the rising edge of ACLK. When control data is being read from the port, the CLC031A will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Data being output from the selected register is driven by the port immediately following the rising edge of ACLK or when the address signal is removed. For optimum system timing, the signals driving the address to the port should be removed
immediately after the address is clocked into the port and before or simultaneously with the falling edge of ACLK at the end of that address cycle. Output data remains stable until the next rising edge of ACLK and may be written into external devices at any time after the removal of the address signal. This second clock resets the port from drive to receive and readies the port for another access cycle. Example: Read the Full-field Flags via the AD port. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-high. 3. Present 001h to AD[9:0] as the register address. 4. 5. 6. Toggle ACLK. Release the bus driving the AD port. Read the data present on the AD port. The Full-field Flags are bits AD[4:0]. 7. Toggle ACLK to release the AD port. Figure 3 shows the sequence of clock and control signals for writing control data to the ancillary/control data port. The control data write mode is similar to the read mode. Control data write mode is invoked by making the ANC/CTRL input low and the RD/WR input low. The 8-bit address of the control register set to be accessed is input to the port on bits AD[7:0]. When a control register write address is being written to the port, AD[9:8] must be driven as 00b (0XXh, where XX are AD[7:0]). The address is captured on the rising edge of ACLK. The address data is removed on the falling edge of ACLK. Next, the control data is presented to the port bits AD[7:0] and written into the selected register on the next rising edge of ACLK. When control data is being written to the port, AD[9:8] must be driven as 11b (3XXh, where XX are AD[7:0]). Control data written into the registers may be read out non-destructively in most cases. Example: Setup (without enabling) the TPG Mode via the AD port using the 1125 line, 30 frame, 74.25MHz, interlaced component (SMPTE 274M) colour bars as test pattern. The TPG may be enabled after setup using the Multi-function I/O port or by the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Dh to AD[9:0] as the Test 0 register address. 4. Toggle ACLK. 5. Present 027h to AD[9:0] as the register data. 6. Toggle ACLK.
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Device Operation
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FIGURE 2. Control Data Read Timing (2 read and 1 write cycle shown)
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FIGURE 3. Control Data Write Timing Ancillary Data Functions The CLC031A can recover Ancillary Data from the serial data stream. This Ancillary Data and related control characters are defined in the relevant SMPTE standards and may reside in the horizontal and vertical blanking intervals. The data can consist of different types of message packets including audio data. The serial Ancillary Data space must be formatted according to SMPTE 291M. The CLC031A supports Ancillary Data in the chrominance channel (C'r/ C'b) only for high-definition operation. Ancillary Data for standard definition follows the requirements of SMPTE 125M. The Ancillary Data FIFO is sized to handle a maximum length ANC data Type 1 or Type 2 packet without the ANC Flag, 259 words. Defined in SMPTE 291M, the packet con13
sists of the Ancillary Data Flag, a 3-word Data ID and Data Count, 255 8- or 10-bit User Data Words and a Checksum. The design of the CLC031A Ancillary Data FIFO also allows storage of up to 8 shorter length messages with total length not exceeding 259 words including all ID information. Ancillary Data is copied from the data stream into the Ancillary Data FIFO. The parallel Ancillary Data will still be present in the parallel chroma output DV[9:0]. ancillary flag information is not extracted into the FIFO. Copying of ANC data from the video data into the FIFO is controlled by the ANC Mask and ANC ID bits in the control registers. A system of flags, ANC FIFO Empty, ANC FIFO 90% Full, ANC FIFO Full and ANC FIFO Overrun are used to monitor FIFO status. The details and functions of these and other control words are explained later in this datasheet.
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CLC031A
Device Operation
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Figure 4 shows the relationship of clock, data and control signals for reading Ancillary Data from the port AD[9:0]. In Ancillary Data read mode, 10-bit Ancillary Data is routed from the Ancillary Data FIFO and read from the port AD[9:0] at a rate determined by ACLK. Ancillary Data read (output) mode is invoked by making the ANC/CTRL input high and the RD/WR input high. Ancillary Data is clocked from the FIFO on the L-H transition of ACLK. Data may be read from the port on rising edges of ACLK, after the specified propagation delay, until the FIFO is emp-
tied. Data may only be read from the port when in the Ancillary Data mode. Ancillary Data cannot be written to the port. To conserve power when the Ancillary Data function is not being used, the internal Ancillary Data FIFO clock is disabled. This clock must be enabled before Ancillary Data may be replicated into the FIFO for output. This internal FIFO clock is controlled by FIFO CLOCK ENABLE, bit-6 of the ANC 5 register (address 17h). The default condition of FIFO CLOCK ENABLE is OFF. After enabling the internal FIFO clock by turning this bit ON, ACLK must be toggled three (3) times to propagate the enable to the clock tree.
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FIGURE 4. Ancillary Data Read Timing MULTI-FUNCTION I/O PORT The multi-function I/O port can be configured to provide immediate access to many control and indicator functions that are stored within the CLC031A's configuration and control registers. The individual pins comprising this port are assigned as input or output for selected functions stored in the control data registers. The multi-function I/O port is configured by way of an 8x6-bit register bank consisting of registers I/O pin 0 CONFIG through I/O pin 7 CONFIG. The contents of these registers determine whether the port bits function as inputs or outputs and to which control function or indicator each port bit is assigned. Port bits may be assigned to access different functions and indicators or any or all port bits may be assigned to access the same function or indicator (output mode only). The same indicator or function should not be assigned to more than one port bit as an input. Controls and indicators that are accessible by the port and their corresponding selection addresses are given in the I/O Pin Configuration Register Addresses, Table 6. Table 2 gives the control register bit assignments. Data resulting from device operation will be sent to the selected I/O port bit. This same data is also stored in the configuration and control registers. Mapping the control and indicator functions in this manner means that device operation will be immediately reflected at the I/O port pins thereby ensuring more reliable real-time operation of the device within and by the host system. When a multifunction I/O port bit is used as input to a control register bit, data must be presented to the I/O port bit and clocked into the register bit using ACLK as shown in Figure 5. Port timing for bit write operations is the same as for the ANC/CTRL port operation.
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FIGURE 5. I/O Port Data Write Timing Example: Program multi-function I/O port bit-0 as the CRC Luma Error bit output. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4. Toggle ACLK. 5. Present 310h to AD[9:0] as the register data. 6. Toggle ACLK. EDH/CRC SYSTEM The CLC031A has EDH and CRC character generation and checking circuitry. The EDH system functions as described in SMPTE Recommended Practice RP-165. The CRC system functions as specified in SMPTE 292M. The EDH/CRC polynomial generators/checkers accept parallel data from the de-serializing system and generate the EDH and CRC check words for comparison with those received in the data. The EDH Enable bit in the control register enables the EDH generation and checking system. Incoming SDTV data is checked for errors and the EDH flags are updated automati14
3.
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CLC031A
Device Operation
(Continued)
cally. EDH errors are reported in the EDH0, EDH1, and EDH2 register sets of the configuration and control registers. Updated or new EDH check words and flags may be generated and inserted in the data. EDH check words are generated using the polynomial X16 + X12 + X6 + 1 per SMPTE RP165. Generation and automatic insertion of new or corrected EDH check words is controlled by EDH Force and EDH Enable bits in the control registers. EDH check words and status flags are inserted in the parallel data at the correct positions in the Ancillary Data space and formatted per SMPTE 291M. After a reset, the initial state of all EDH and CRC check characters is 00h. The SMPTE 292M high definition video standard employs CRC (cyclic redundancy check codes) error checking instead of EDH. The CRC consists of two 18-bit words generated using the polynomial X18 + X5 + X4 + 1 per SMPTE 292M. One CRC is used for luminance and one for chrominance data. The CRCs appear in the data stream following the EAV and line number characters. The CRCs are checked and errors are reported in the EDH0, EDH1, and EDH2 register sets of the configuration and control registers. PHASE-LOCKED LOOP / CLOCK-DATA RECOVERY SYSTEM The phase-locked loop and clock-data recovery (PLL/ CDR) system generates all internal timing and data rate clocks for the CLC031A. The PLL/CDR system consists of five main functional blocks: 1) the input buffer which receives the incoming data, 2) input data samplers which oversample the data coming from the input buffer, 3) a PLL (VCO, divider chain, phase-frequency detector and internal loop filter) which generates sampling and other system clocks, 4) a digital CDR system to recover the oversampled serial input data from the samplers and the digital system control and 5) a rate detect controller which sequences the PLL to find the data rate. Using an oversampling technique, the timing information encoded in the serial data is extracted and used to synchronize the recovered clock and data. The parallel data rate and other clock signals are derived from the regenerated serial clock. The parallel data rate clock is 1/10th of the serial data rate clock for standard definition or 1/20th of the serial data clock frequency for high definition. The data interface between the CDR and the digital processing block uses 10-bit data plus the required clocks. The PLL is held in coarse frequency lock by an external 27MHz clock signal, EXT CLK, or by an external 27MHz crystal and internal oscillator. Upon power-on, EXT CLK is the default reference. The internal oscillator and an external crystal may be used as the reference by setting the OSCEN bit in the CDR register. The reference clock reduces lock latency and enhances format and auto-rate detection robust-
ness. PLL acquisition, data phase alignment and format detection time is 20ms or less at 1.485Mbps. The VCO has separate VDDPLL and VSSPLL power supply feeds, pins 51 and 52, which may be supplied power via an external lowpass filter, if desired.
20020105
FIGURE 6. Crystal and Load Circuit A 27MHz crystal and load circuit may be used to provide the reference clock. A fundamental mode crystal with the following parameters is used: frequency 27MHz, frequency tolerance 30ppm, load capacitance 18pF, maximum drive level 100W, equivalent series resistance < 50, operating temperature range 0C to 70C. Refer to Figure 6 for a typical load circuit and connection information. The CLC031A indicates that the PLL is locked to the incoming data rate and that the CDR has acquired a phase of the serial data by setting the Lock Detect bit in the Video Info 0 control register. Indication of the standard being processed is retained in the FORMAT[4:0] bits in the FORMAT 1 control data register. Format data from this register can be programmed for output on the multi-function I/O port. The power-on default assigns Lock Detect as I/O Port bit 4. POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT The CLC031A requires two power supplies, 2.5V for the core logic functions and 3.3V for the I/O functions. The supplies must be applied to the device in proper sequence. The 3.3V supply must be applied prior to or coincident with the 2.5V supply. Application of the 2.5V supply must not precede the 3.3V supply. It is recommended that the 3.3V supply be configured or designed so as to control application of the 2.5V supply in order to satisfy this sequencing requirement. The CLC031A has an automatic, power-on-reset circuit. Reset initializes the device and clears TRS detection circuitry, all latches, registers, counters and polynomial generators/checkers and resets the EDH/CRC characters to 00h. An active-HIGH-true, manual reset input is available at pin 49. The reset input has an internal pull-down device and may be considered inactive when unconnected. Important: When power is first applied to the device or following a reset, the ancillary and Control Data Port must be initialized to receive data. This is done by toggling ACLK three times.
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CLC031A
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(Continued)
TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST) The CLC031A includes an on-board, parallel video test pattern generator (TPG). Four test pattern types are available in both HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-colour vertical bar pattern. The pathologicals follow recommendations contained in SMPTE RP 178-1996 regarding the test data used. The colour bar pattern has optional bandwidth limiting coding in the chroma and luma data transitions between bars. The VPG FILTER ENABLE bit in the VIDEO INFO 0 control register enables the colour bar filter function. The test pattern data is available at the video data outputs, DV[19:0] with a corresponding parallel rate clock, VCLK, appropriate to the particular standard and format selected. The TPG also functions as a built-in self-test (BIST) which can be used to verify device functionality. The BIST function performs a comprehensive go/no-go test of the device. The test may be run using any of the HD colour bar patterns or one of two SD patterns, either the 270 Mb/s NTSC colour bar or the PAL PLL pathological, as the test data pattern. Data is input from the digital processing block, processed through the device and tested for errors using either the EDH system for SD or the CRC system for HD. Clock signals from the CDR block supply timing for the test data. The CDR must be supplied a 27MHz reference clock via the XTALi/Ext Clk input (or using the internal oscillator and crystal) during the TPG or BIST function. A go/no-go indication is logged in the Pass/Fail bit of the TEST 0 control register set. This bit may be assigned as an output on the multifunction I/O port. TPG and BIST operation is initiated by loading the code for the desired test pattern into the Test Pattern Select[5:0] bits and by setting the TPG Enable bit of the TEST 0 register. Note that when attempting to use the TPG or BIST immediately after the device has been reset or powered on, the TPG defaults to the 270Mbps SD rate. The device must be configured for the desired test pattern by loading the appropriate code in to the TEST 0 register. If HD operation is desired,
selection of the desired HD test pattern is sufficient to enable the device to configure itself to run at the correct rate and generate valid data. Table 5 gives the available test patterns and codes. The Pass/Fail bit in the control register gives the device test status indication. If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected in the internal circuitry of the CLC031A, Pass/Fail will remain reset to a logic-0. TPG or BIST operation is stopped by resetting the TPG Enable bit. Parallel output data is present at the DV[19:0] outputs during TPG or BIST operation. Example: Enable the TPG Mode to use the NTSC 270Mbps colour bars as the BIST and TPG pattern. Enable TPG operation using the I/O port. Set ANC/CTRL to a logic-low. Set RD/WR to a logic-low. Present 00Dh to AD[9:0] as the TEST 0 register address. 4. Toggle ACLK. 5. Present 343h to AD[9:0] as the register data (525 line, 30 frame, 27MHz, NTSC 4x3, colour bars (SMPTE 125M)). 6. Toggle ACLK. 7. The PASS/FAIL indicator, TEST 0 register, Bit 7, should be read for the result of the test. Alternatively, this bit may be mapped to a convenient bit of the Multi-function I/O bus. The test pattern data and clock is available at the DV[19:0] and VCLK outputs. CONFIGURATION AND CONTROL REGISTERS The configuration and control registers store data which determines the operational modes of the CLC031A or which result from its operation. Many of these registers may be assigned as external I/O functions which are then available on the multi-function I/O bus. These functions are summarized in Table 1 and detailed in Table 2. The power-on default condition for the multi-function I/O port is indicated in Table 1 and detailed in Table 6. 1. 2. 3.
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Register Function EDH and CRC Operations CRC Error (SD/HD) CRC Error Luma CRC Error Chroma CRC Replace Full-Field Flags Active Picture Flags ANC Flags EDH Force EDH Enable F/F Flag Error A/P Flag Error ANC Flag Error Ancillary Data Operations ANC Checksum Force ANC Checksum Error ANC FIFO Empty ANC FIFO 90% Full ANC FIFO Full ANC FIFO Overrun ANC ID ANC Mask MSG Track MSG Flush Static FIFO Flush Static Full MSG Available Short MSG Detect FIFO Clock Enable FIFO Extract Enable Video FIFO Operation Video FIFO Depth Video Format Operations Format Set SD Only HD Only Format H V F Framing Mode Framing Enable New Sync Position (NSP) SAV EAV De-scramble Enable NRZI Enable
(Continued) TABLE 1. Configuration and Control Data Register Summary Bits Read or Write Initial Condition Available on I/O Bus Output Output Output No No No No Input Input Output Output Output Input Output Output Output Output Output No No No No No Output Output No Input No No No No Output Output Output Output ON ON No Input Output Output Output ON ON No No (Note 11) I/O 7 Format [4] (Note 11) I/O 3 (Note 11) I/O 2 (Note 11) I/O 1 (Note 11) I/O 0 (Note 11) I/O 6 (Note 13) Notes
1 1 1 1 5 5 5 1 1 1 1 1 1 1 1 1 1 1 16 16 1 1 1 1 1 1 1 3 5 1 1 5 1 1 1 1 1 1 1 1 1 1
R R R R/W R R R R/W R/W R R R R/W R R R R R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R R R R/W R/W R R R R/W R/W
Reset Reset Reset OFF Reset Reset Reset OFF ON Reset Reset Reset OFF Reset Set Reset Reset Reset 0000h FFFFh OFF OFF OFF OFF OFF OFF OFF 000b 00000B OFF OFF
(Note 11) I/O 5
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Register Function LSB Clipping Enable Sync Detect Enable De-Dither Enable Vert. De-Dither Enable Lock Detect Unscrambled Video Data Out TPG and BIST Operations Test Pattern Select TPG Enable Pass/Fail VPG Filter Enable Reference Clock Operations Reference Clock External Vclk I/O Bus Pin Config.
(Continued)
TABLE 1. Configuration and Control Data Register Summary (Continued) Bits 1 1 1 1 1 1 Read or Write R/W R/W R/W R/W R R/W OFF Initial Condition ON ON OFF OFF Available on I/O Bus No No Input Input Output No (Note 11) I/O 4 (Note 13) Notes
6 1 1 1 2 1 48
R/W R/W R R/W R/W R/W R/W
000000b OFF OFF 00b OFF See Table 6
Input Input Output Input No No No
525/27 MHz/Black
EXT CLK Enabled (Note 13)
Multifunction I/O Bus Operations
Note 11: Connected to multifunction I/O port at power-on. Note 12: ON = SET = logic-1, OFF = RESET = logic-0 (positive logic). Note 13: Special or restricted functionality. Refer to text for details.
TABLE 2. Control Register Bit Assignments Bit 7 CRC ERROR CRC REPLACE F/F FLAG ERROR Bit 6 EDH FORCE CRC ERROR LUMA A/P FLAG ERROR Bit 5 EDH ENABLE CRC ERROR CHROMA ANC FLAG ERROR Bit 4 F/F UES Bit 3 F/F IDA Bit 2 F/F IDH Bit 1 F/F EDA Bit 0 F/F EDH
EDH 0 (register address 01h) EDH 1 (register address 02h) A/P UES A/P IDA A/P IDH A/P EDA A/P EDH
EDH 2 (register address 03h) ANC UES ANC IDA ANC IDH ANC EDA ANC EDH
ANC 0 (register address 04h) VIDEO VIDEO VIDEO FIFO-DEPTH(2) FIFO-DEPTH(1) FIFO-DEPTH(0) ANC 1 (register address 05h) ANC ID(7) ANC ID(15) ANC ID(6) ANC ID(14) ANC ID(5) ANC ID(13) ANC ID(4) ANC ID(12) ANC MASK(4) ANC MASK(12) ANC ID(3) ANC ID(11) ANC MASK(3) ANC MASK(11) ANC ID(2) ANC ID(10) ANC MASK(2) ANC MASK(10) ANC ID(1) ANC ID(9) ANC MASK(1) ANC MASK(9) ANC ID(0) ANC ID(8) ANC MASK(0) ANC MASK(8) ANC 2 (register address 06h) ANC 3 (register address 07h) ANC MASK(7) ANC MASK(6) ANC MASK(5) ANC FIFO OVERRUN ANC FIFO EMPTY ANC FIFO FULL ANC CHECK- ANC CHECKSUM ERROR SUM FORCE
ANC 4 (register address 08h) ANC MASK(15) FIFO EXTRACT ENABLE ANC MASK(14) ANC MASK(13)
ANC 5 (register address 17h) FIFO CLOCK ENABLE FULL MSG AVAILABLE reserved FIFO FLUSH STATIC reserved MSG FLUSH STATIC MSG TRACK
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Bit 7 ANC FIFO 90% FULL FRAMING MODE F Bit 6 SHORT MSG DETECT
(Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 5 ANC PARITY MASK Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ANC 6 (register address 18h) reserved reserved reserved reserved VANC
FORMAT 0 (register address 0Bh) SD ONLY HD ONLY FORMAT SET(4) FORMAT(4) TEST PATTERN SELECT(4) FORMAT SET(3) FORMAT(3) TEST PATTERN SELECT(3) FORMAT SET(2) FORMAT(2) TEST PATTERN SELECT(2) FORMAT SET(1) FORMAT(1) TEST PATTERN SELECT(1) FORMAT SET(0) FORMAT(0) TEST PATTERN SELECT(0)
FORMAT 1 (register address 0Ch) V H TEST PATTERN SELECT(5) TEST 0 (register address 0Dh) PASS/FAIL TPG ENABLE
VIDEO INFO 0 (register address 0Eh) DE-DITHER ENABLE VERT. DE-DITHER ENABLE EXTERNAL VCLK reserved VPG FILTER ENABLE LOCK DETECT EAV SAV NSP FRAMING ENABLE
VIDEO CONTROL 0 (register address 55h) reserved SYNC DETECT ENABLE reserved LSB CLIP ENABLE reserved reserved NRZI ENABLE INT_OSC EN DE-Scramble ENABLE CLK EN reserved
REFERENCE CLOCK (register address 67h) reserved reserved reserved MULTI-FUNCTION I/O BUS PIN CONFIGURATION I/O PIN 0 CONFIG (register address 0Fh) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved PIN 0 SEL[5] PIN 1 SEL[5] PIN 2 SEL[5] PIN 3 SEL[5] PIN 4 SEL[5] PIN 5 SEL[5] PIN 6 SEL[5] PIN 7 SEL[5] PIN 0 SEL[4] PIN 1 SEL[4] PIN 2 SEL[4] PIN 3 SEL[4] PIN 4 SEL[4] PIN 5 SEL[4] PIN 6 SEL[4] PIN 7 SEL[4] PIN 0 SEL[3] PIN 1 SEL[3] PIN 2 SEL[3] PIN 3 SEL[3] PIN 4 SEL[3] PIN 5 SEL[3] PIN 6 SEL[3] PIN 7 SEL[3] PIN 0 SEL[2] PIN 1 SEL[2] PIN 2 SEL[2] PIN 3 SEL[2] PIN 4 SEL[2] PIN 5 SEL[2] PIN 6 SEL[2] PIN 7 SEL[2] PIN 0 SEL[1] PIN 1 SEL[1] PIN 2 SEL[1] PIN 3 SEL[1] PIN 4 SEL[1] PIN 5 SEL[1] PIN 6 SEL[1] PIN 7 SEL[1] PIN 0 SEL[0] PIN 1 SEL[0] PIN 2 SEL[0] PIN 3 SEL[0] PIN 4 SEL[0] PIN 5 SEL[0] PIN 6 SEL[0] PIN 7 SEL[0] I/O PIN 1 CONFIG (register address 10h) I/O PIN 2 CONFIG (register address 11h) I/O PIN 3 CONFIG (register address 12h) I/O PIN 4 CONFIG (register address 13h) I/P PIN 5 CONFIG (register address 14h) I/O PIN 6 CONFIG (register address 15h) I/O PIN 7 CONFIG (register address 16h)
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Register Name EDH 0 EDH 1 EDH 2 ANC 0 ANC 1 ANC 2 ANC 3 ANC 4 ANC 5 ANC 6 FORMAT 0 FORMAT 1 TEST 0 VIDEO INFO 0 I/O PIN 0 CONFIG I/O PIN 1 CONFIG I/O PIN 2 CONFIG I/O PIN 3 CONFIG I/O PIN 4 CONFIG I/O PIN 5 CONFIG I/O PIN 6 CONFIG I/O PIN 7 CONFIG VIDEO CONTROL 0 VIDEO CONTROL 1 REFERENCE CLOCK
(Continued)
TABLE 3. Control Register Addresses Address Hexadecimal 01 02 03 04 05 06 07 08 17 18 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 55 56 67
Specific types of CRC errors in incoming HD serial data are reported in the CRC ERROR LUMA and CRC ERROR CHROMA bits. The CRC REPLACE bit, when set, causes the CRCs in the incoming data to be replaced with CRCs calculated by the CLC031A. The bit is normally reset (OFF). EDH 2 (register 03h) The EDH Ancillary Data flags ANC UES, ANC IDA, ANC IDH, ANC EDA andANC EDH are defined in SMPTE RP 165. The flags are updated automatically when the EDH function is enabled and data is being received. The status of EDH flag errors in incoming SD serial data are reported in the ffFlagError, apFlagError and ancFlagError bits. Each of these bits is the logical-OR of the corresponding EDH and EDA flags. ANC 0 (Address 04h) The V FIFO Depth[2:0] bits control the depth of the video FIFO which preceeds the parallel output data drivers. The depth can be set from 0 to 4 stages by writing the corresponding binary code into these bits. For example: to set the Video FIFO depth at two registers, load 11010XXXXXb into the ANC 0 control register (where X represents the other functional bits of this register). Note: When changing some but not all bits in a register and to retain unchanged other data previously stored in the register, read the register's contents and logically-OR this with the new data. Then write the modified data back into the register. Flags for ANC FIFO EMPTY, ANC FIFO 90% FULL, ANC FIFO FULL and ANC FIFO OVERRUN are available in the configuration and control register set. These flags can also be assigned as outputs on the multi-function I/O port. ANC FIFO EMPTY when set indicates that the FIFO contains no data. ANC FIFO 90% FULL indicates when the FIFO is at 90% of capacity. Since it is virtually impossible for the host processor to begin extracting data from the FIFO after it has been flagged as full without the possibility of an overrun condition occurring, ANC FIFO 90% FULL is used as an advanced command to the host to begin extracting data from the FIFO. To be used properly, ANC FIFO 90% FULL should be assigned as an output on the multi-function I/O port and monitored by the host system. Otherwise, inadvertent loss of ancillary packet data could occur. ANC FIFO FULL when set indicates that the FIFO registers are completely filled with data. The ANC FIFO OVERRUN flag indicates that an attempt to write data into a full FIFO has occurred. ANC FIFO OVERRUN can be reset by reading the bit's status via the ancillary/ Control port. If an overrun occurrs, the status of the FIFO message tracking will be invalidated. In this event, the FIFO should be flushed to reset the message tracking pointers. Any messages then in the FIFO will be lost. The ANC Checksum Force bit, under certain conditions, enables the overwriting of Ancillary Data checksums received in the data. Calculation and insertion of new Ancillary Data checksums is controlled by the ANC Checksum Force bit. If a checksum error is detected (calculated and received checksums do not match) and the ANC Checksum Force bit is set, the ANC Checksum Error bit is set and a new checksum is inserted in the Ancillary Data replacing the previous one. If a checksum error is detected and the ANC Checksum Force bit is not set, the checksum mismatch is
EDH 0 (register 01h) The EDH Full-Field flags F/F UES, F/F IDA, F/F IDH, F/F EDA andF/F EDH are defined in SMPTE RP 165. The flags are updated automatically when the EDH function is enabled and data is being received. The EDH ENABLE bit, when set, enables operation of the EDH generator function during SD operation. The default condition of this bit is set (ON). The EDH FORCE bit, when set, causes updated EDH packets to be inserted in the parallel output data regardless of the previous condition of EDH checkwords and flags in the input serial data. This function may be used in situations where video content has been edited thus making the previous EDH information invalid. The default condition of this bit is reset (OFF). The CRC ERROR bit indicates that errors in either the EDH checksums (SD) or CRC checkwords (HD) were detected in the serial input data. This bit is a combined function which indicates the presence of either EDH errors during SD operation or CRC errors during HD operation. EDH 1 (register 02h) The EDH Active Picture flags A/P UES, A/P IDA, A/P IDH, A/P EDA andA/P EDH are defined in SMPTE RP 165. The flags are updated automatically when the EDH function is enabled and data is being received.
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CLC031A
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(Continued)
reported via the ANC Checksum Error bit. ANC Checksum Error is available as an output on the multifunction I/O port. ANC 1 AND 2 (Addresses 05h and 06h) The extraction of Ancillary Data packets from video data into the FIFO is controlled by the ANC MASK[15:0] and ANC ID[15:0] bits in the control registers. The ANC ID[7:0] register normally is set to a valid 8-bit code used for component Ancillary Data packet DID identification as specified in SMPTE 291M-1998. Similarly, ANC ID[15:8] normally is set to a valid 8-bit code used for component Ancillary Data packet SDID/DBN identification. ANC 3 AND 4 (Addresses 07h and 08h) The ANC MASK[7:0] is an 8-bit word that can be used to selectively control extraction of packets with specific DIDs (or DID ranges) into the FIFO. When the ANC MASK[7:0] is set to FFh, packets with any DID can be extracted into the FIFO. When any bit or bits of the ANC MASK[7:0] are set to a logic-1, the corresponding bit or bits of the ANC ID[7:0] are a don't-care when matching DIDs of packets being extracted. When the ANC MASK[7:0] is set to 00h, the ANC DID of incoming packets must match exactly, bit-for-bit the ANC ID[7:0] set in the control register for the packets to be extracted into the FIFO. The initial value of the ANC MASK[7:0] is FFh and the ANC ID[7:0] is 00h. Similarly, ANC MASK[15:8] is an 8-bit word that can be used to selectively control extraction of packets with specific SDID/DBN (or SDID/DBN ranges) into the FIFO. Operation and use of these bits is the same as for ANC MASK[7:0] previously discussed. ANC 5 (Address 17h) The FIFO EXTRACT ENABLE bit in the control registers enables the device to extract or copy Ancillary Data from the video data stream and place it in the ANC FIFO. From there data may be output via the parallel ancillary port. Data extraction is enabled when this bit is set to a logic-1. This bit can be used to delay automatic extraction and therefore the output of parallel Ancillary Data. FIFO EXTRACT ENABLE should be asserted during an SAV or EAV to avoid timing problems with Ancillary Data extraction. Access to data in the FIFO is controlled by the RD/WR, ANC/CTRL and ACLK control signals. To conserve power when the Ancillary Data function is not being used, the internal Ancillary Data FIFO clock is disabled. This clock must be enabled before Ancillary Data may be replicated into the FIFO for output. FIFO CLOCK ENABLE, bit-6 of the ANC 5 register (address 17h), when set, enables this clock to propagate to the FIFO. The default condition of FIFO CLOCK ENABLE is OFF. After enabling the internal FIFO clock by turning this bit ON, ACLK must be toggled three (3) times to propagate the enable to the clock tree. ACLK should remain running at all times when the ANC FIFO is in use. Otherwise, message tracking and related functions will not operate correctly. The CLC031A can keep track of up to 8 ANC data packets in the ANC FIFO. Incoming packet length versus available space in the FIFO is also tracked. The MSG TRACK bit in the control registers, when set, enables tracking of packets in the FIFO. Other functions for control of packet traffic in the
FIFO are FIFO FLUSH STAT and MSG FLUSH STAT. If the user wishes to handle more than 8 messages, the MSG TRACK bit should be turned off (reset). The operation FIFO FLUSH STAT will no longer work and the function FULL MSG AVAILABLE will no longer be a reliable indicator that messages are available in the FIFO. The user may still effectively use the FIFO by monitoring the states of ANC FIFO EMPTY, ANC FIFO FULL, ANC FIFO 90%FULL and ANC FIFO OVERRUN. Setting the FIFO FLUSH STAT bit to a logic-1 flushes the FIFO. FIFO FLUSH STAT may not be set while the FIFO is being accessed (Read or Write). FIFO FLUSH STAT is automatically reset after this operation is complete. When MSG FLUSH STAT is set to a logic-1, the oldest message packet in the FIFO is flushed when data is not being written to the FIFO. MSG FLUSH STAT is automatically reset after this operation is complete. The FULL MSG AVAILABLE bit in the control registers, when set, notifies the host system that complete packets reside in the Ancillary Data FIFO. When this bit is not set, the messages in the FIFO are incomplete or partial. This function is not affected by MSG TRACK. The FULL MSG AVAILABLE function is most useful when mapped to the multifunction I/O port as an output. ANC 6 (Address 18h) The ANC FIFO 90% FULL flag bit indicates when the ANC FIFO is 90% full. This bit may be mapped to the multifunction I/O port. The purpose of this flag is to provide a signal which gives the host system time to begin reading from the FIFO before it has the chance to overflow. This was done because it is virtually impossible to monitor the FIFO FULL flag and begin extracting from the FIFO before an overrun condition occurs. The SHORT MSG DETECT flag bit indicates when short ANC messages have been detected. i.e. An ANC header was detected before the last full message was recovered. This bit may be mapped to the multi-function I/O port. The ANC PARITY MASK bit when set disables parity checking for DID and SDID words in the ANC data packet. When reset, parity checking is enabled; and, if a parity error occurs, the packet will not be extracted. The VANC bit, when set, enables extraction of ANC data present in the vertical blanking interval (both active video and horizontal blanking portions of the line). FORMAT 0 (Address 0Bh) The CLC031A may be set to process a single video format by writing the appropriate data into the FORMAT 0 register. The Format Set[4:0] bits confine the CLC031A to recognize and process only one of the fourteen specified type of SD or HD formats defined by a particular SMPTE specification. The Format Set[4:0] bits may not be used to confine device operation to a range of standards. The available formats and codes are detailed in Table 4. Generally speaking, the Format Set[4:0] codes indicate or group the formats as follows: Format Set[4] is set for the HD data formats, reset for SD data formats. Format Set[3] is set for PAL data formats (with the exception of the SMPTE 274M 24-frame progressive format), reset for NTSC data formats. Format Set[2:0] further sub-divide the standards as given in the table.
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Format Code [4,3,2,1,0] 00001 00010 00011 01001 01010 01011 10001 10010 10011 11001 11010 11100 11101 10100
(Continued) TABLE 4. Video Raster Format Parameters
Format SDTV, 54 SDTV, 36 SDTV, 27 SDTV, 54 SDTV, 36 SDTV, 27 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25 HDTV, 74.25
Spec. RP 174 SMPTE 267 SMPTE 125 ITU-R BT 601.5 ITU-R BT 601.5 ITU-R BT 601.5 SMPTE 260 SMPTE 274 SMPTE 274 SMPTE 274 SMPTE 274 SMPTE 295 SMPTE 274 SMPTE 296 (1, 2)
Frame Rate 60I 60I 60I 50I 50I 50I 30I 30I 30P 25I 25P 25I 24P 60P
Lines 525 525 525 625 625 625 1125 1125 1125 1125 1125 1250 1125 750
Active Lines 507/487* 507/487* 507/487* 577 577 577 1035 1080 1080 1080 1080 1080 1080 720
Samples 3432 2288 1716 3456 2304 1728 2200 2200 2200 2640 2640 2376 2750 1650
Active Samples 2880 1920 1440 2880 1920 1440 1920 1920 1920 1920 1920 1920 1920 1280
The HD Only bit when set to a logic-1 locks the CLC031A into the high definition data range and frequency. In systems designed to handle only high definition signals, enabling HD Only reduces the time required for the CLC031A to establish frequency lock and determine the HD format being processed. The SD Only bit when set to a logic-1 locks the CLC031A into the standard definition data ranges and frequencies. In systems designed to handle only standard definition signals, enabling SD Only reduces the time required for the CLC031A to establish frequency lock and determine the format being processed. When SD Only and HD Only are set to logic-0, the device operates in SD/HD mode. The Framing Mode bit in the Format 0 register and Framing Enable in the Video Info 0 register combine with Framing Enable to control the manner in which the CLC031A aligns framing. When Framing Mode and Framing Enable are both reset, the CLC031A aligns on the first valid TRS character. If another TRS occurs that is not on a word boundary, the NSP bit is set until the next TRS that is on a word boundary occurs. When Framing Mode is set to a logic-1, the CLC031A operates similarly to the CLC011 when NSP is tied to FE. An alternative configuration that operates identically can be achieved with the CLC031A by mapping NSP as an output and Framing Enable as an input on the Multifunction I/O bus and externally connecting them. In this case Framing Mode should be reset to a logic-0. When Framing Mode is reset and Framing Enable is set, the CLC031A realigns on every valid TRS. The initial state of Framing Mode is set following a reset or at power-on. FORMAT 1 (Address 0Ch) The CLC031A automatically determines the format of the incoming serial data. The result of this operation is stored in the FORMAT 1 register. The Format[4:0] bits identify which
of the many possible video data standards that the CLC031A can process is being received. These format codes follow the same arrangement as for the Format Set[4:0] bits. These formats and codes are given in Table 4. Bit Format[4] when set indicates that HD data is being processed. When reset, SD data is indicated. Format[3] when set indicates that PAL data is being processed. When reset NTSC data is being processed. Format[2:0] correspond with one of the sub-standards given in the table. Note that the CLC031A does not distinguish or log the data rate differences between HD data at 74.25Mhz and 74.25MHz/1.001. The H, V, and F bits correspond to input TRS data bits 6, 7 and 8, respectively. The meaning and function of this data is the same for both standard definition (SMPTE 125M) and high definition (SMPTE 292M luminance and colour difference) video data. Polarity is logic-1 equals HIGH-true. These bits are registered for the duration of the applicable field. TEST 0 REGISTER (Address 0Dh) The Test Pattern Select bits determine which test pattern is output when the Test Pattern Generator (TPG) mode or the Built-in Self-Test (BIST) mode is enabled. Table 5 gives the codes corresponding to the various test patterns. All HD colour bar test patterns are inherently BIST data. BIST test patterns for SD are: NTSC, 27MHz, 4x3 Colour Bars and PAL, 27MHz, 4x3 PLL Pathological. The TPG Enable bit when set to a logic-1 enables the Test Pattern Generator function and built-in self-test (BIST). The Pass/Fail bit indicates the result of the built-in self-test. This bit is a logic-1 for a pass condition.
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CLC031A
Device Operation
(Continued) TABLE 5. Test Pattern Selection Codes
Test Pattern Select Word Bits >
Bit 5 1=HD
Bit 4 1=Progressive 0=Interlaced 1=PAL 0=NTSC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 3
Bit 2
Bit 1 00=Black 01=PLL Path. 10=EQ Path. 11=Colour Bars
Bit 0
Video Raster Standard
0=SD
1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Interlaced Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Interlaced Component (SMPTE 295M)
1125 Line, 74.25 MHz, 30 Frame Progressive Component (SMPTE 274M)
1125 Line, 74.25 MHz, 25 Frame Progressive Component (SMPTE 274M)
1125 Line, 74.25 MHz, 24 Frame Progressive Component (SMPTE 274M)
750 Line, 74.25 MHz, 60 Frame Progressive Component (SMPTE 296M)
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CLC031A
Device Operation
(Continued) TABLE 5. Test Pattern Selection Codes (Continued)
Test Pattern Select Word Bits > Ref. Black PLL Path. EQ Path. Colour Bars (SD BIST) Ref. Black PLL Path. (SD BIST) EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars Ref. Black PLL Path. EQ Path. Colour Bars 525 Line, 30 Frame, 54 MHz (NTSC) Ref. Black PLL Path. EQ Path. Colour Bars 625 Line, 25 Frame, 54 MHz (PAL) Ref. Black PLL Path. EQ Path. Colour Bars
Bit 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)
625 Line, 25 Frame, 27 MHz, PAL 4x3 (ITU-T BT.601)
525 Line, 30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)
625 Line, 25 Frame, 36 MHz, PAL 16x9 (ITU-T BT.601)
Note: BIST test patterns for SD are: NTSC 4x3 Colour Bars and PAL 4x3 PLL Pathological.
VIDEO INFO 0 REGISTER (Address 0Eh) Re-synchronization of the parallel video output data with the parallel rate clock is controlled by the functions Framing Enable, Framing Mode and NSP. For operating details about these control bits, refer to the preceeding section about Format Registers 0 and 1 and the Format Mode bit. Framing Enable may be assigned as an input on the multifunction I/O port. The NSP (New Sync Position) bit indicates that a new or out-of-place TRS character has been detected in the input data. This bit is set to a logic-1 and remains set for at least one horizontal line period or unless re-activated by a subsequent new or out-of-place TRS. It is reset by an EAV TRS character. The EAV (end of active video) and SAV (start of active video) bits track the occurrence of the corresponding TRS characters. The Lock Detect is a logic-1 when the loop is locked and the CDR has acquired a phase of the incoming serial data. This
bit may be programmed as an output on the multi-function I/O bus. This bit is mapped to I/O port bit 4 in the default condition. The VPG Filter Enable bit when set enables operation of the Video Pattern Generator filter. Operation of this filter causes the insertion of transition codes in the chroma and luma data of colour bar test patterns where these patterns change from one bar to the next. This filter reduces the magnitude of out-of-band frequency products which are produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture monitors. The CLC031A incorporates circuitry that implements a method for handling data that has been subjected to LSB dithering. Data from the de-scrambler is routed for dedithering. Control of this circuitry is via the De-Dither Enable bit in the VIDEO INFO 0 control register. Recovery of data that has been dithered during the vertical blanking interval can be selectively enabled by use of the V De-Dither Enable bit in the VIDEO INFO 0 control register. The initial condition of De-Dither Enable and V De-Dither Enable is OFF.
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CLC031A
Device Operation
(Continued)
VIDEO CONTROL 0 (register address 55h) The EXTERNAL VCLK bit is a special application function which enables use of an external VCXO as a substitute for the internally generated VCLK. Additional circuitry is enabled within the CLC031A which provides phase-frequency detection and control voltage output for the VCXO. An external loop filter and voltage amplifier are required to interface the control voltage output to the VCXO frequency control input. When this function is used, the RBB output function is changed from the bias supply output to the control voltage output of the phase-frequency detector. The VCLK output changes function, becoming the input for the VCXO signal. Use of this function and required external support circuitry is explained in the Section Application Information section. The SYNC DETECT ENABLE bit, when set, enables detection of TRS characters. This bit is normally set (ON). The LSB CLIP ENABLE bit, when set, causes the two LSBs of TRS characters to be set to 00b as described in ITU-R BT.601. This function is normally set (ON). The NRZI ENABLE bit, when set, enables data to be converted from NRZI to NRZ. This bit is normally set (ON). The DE-SCRAMBLE ENABLE bit, when set, enables descrambling of the incoming data according to requirements of SMPTE 259M or SMPTE 292M. This bit is normally set (ON). CAUTION: The default state of this register is 36h. If any of the normal operating features of the descrambler are turned off, this register's default data must be restored to resume normal device operation. REFERENCE CLOCK REGISTER (Address 67h) The Reference Clock register controls operation of the CDR reference clock source. The CLKEN bit when reset to a logic-0 enables the oscillator signal to be used by the
CLC031A as a reference. The default state of this bit at power-on is enabled. In general, this function and bit should not be disabled. The INT_OSC EN bit enables the internal crystal oscillator amplifier. By default this bit is a logic-0 and is therefore inactive at power-on. The device expects an external 27MHz reference reference clock source to be connected to the XTALi/Ext Clk pin and activated at power-on. I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The I/O Pin Configuration Registers are used to map individual bits of the multi-function I/O port to selected bits of the Configuration and Control Registers. Table 6 gives the pin select codes for the Configuration and Control register functions that may be mapped to the port. Pin[n] Select [5] controls whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured as outputs and vice versa. The remaining five Pin[n] Select [4:0] bits identify the particular Control Register bit to be mapped. Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG register address. 4. Toggle ACLK. 5. Present 310h to AD[9:0] as the register data, the bit address of the CRC Luma Error bit in the control registers. 6. Toggle ACLK.
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CLC031A
Device Operation
Register Bit reserved FF Flag Error AP Flag Error ANC Flag Error CRC Error (SD/HD) ANC FIFO 90% FULL SHORT MSG DETECT FULL MSG AVAIL SAV EAV NSP CRC Luma Error CRC Chroma Error F V H Format[0] Format[1] Format[2] Format[3] Format[4] FIFO Full FIFO Empty Lock Detect Pass/Fail FIFO Overrun ANC Chksum Error EDH Force Test Pattern Select[0] Test Pattern Select[1] Test Pattern Select[2] Test Pattern Select[3] Test Pattern Select[4] Test Pattern Select[5] EDH Enable TPG Enable VPG Filter Enable De-Dither Enable Framing Enable FIFO Extract Enable
(Continued)
TABLE 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping Pin[n] SEL[5:0] Codes [5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 [4] 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 [3] 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 [2] 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 [1] 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 [0] 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 HEX 00 01 02 03 04 07 08 09 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 2C 2D 2E 2F I/P or O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P O/P I/P I/P I/P I/P I/P I/P I/P I/P I/P I/P I/P I/P I/P I/O Port Bit 6 I/O Port Bit 4 I/O Port Bit 3 (SD/HD) I/O Port Bit 0 I/O Port Bit 1 I/O Port Bit 2 I/O Port Bit 7 I/O Port Bit 5 Power-On Status
Addresses 05h and 06h are reserved
Addresses 0Ah through 0Ch are reserved
Addresses 29h through 2Bh are reserved
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CLC031A
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 AD9 AD8 AD7 AD6 AD5 VSSD AD4 AD3 AD2 AD1 AD0 VDDD ACLK IO7 IO6 IO5 IO4 IO3 IO2 VSSIO DV19 DV18 DV17 DV16 DV15 VDDIO DV14 DV13 DV12 DV11 DV10 VSSD VDDD DV9 DV8 DV7 DV6 DV5 VSSD DV4 DV3 DV2 DV1 DV0 IO1 IO0 VSSIO VDDIO RESET Name Description Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Negative Power Supply Input (2.5V supply, Digital Logic) Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Ancillary Data Output, Control Data Input Positive Power Supply Input (2.5V supply, Digital Logic) ancillary/Control Clock Input Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Multi-Function I/O Port Negative Power Supply Input (3.3V supply, I/O) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Positive Power Supply Input (3.3V supply, I/O) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Parallel Video Output (HD=Luma) Negative Power Supply Input (2.5V supply, Digital Logic) Positive Power Supply Input (2.5V supply, Digital Logic) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Negative Power Supply Input (2.5V supply, Digital Logic) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Parallel Video Output (HD=Chroma, SD=Luma & Chroma) Multi-Function I/O Port Multi-Function I/O Port Negative Power Supply Input (3.3V supply, I/O) Positive Power Supply Input (3.3V supply, I/O) Manual Reset Input (High True)
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CLC031A
Pin Descriptions
Pin 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VCLK VDDPLL VSSPLL RREF RBB VSSSI SDI SDI VDDSI VSSIO
(Continued) Description Parallel Video Data Clock Output Positive Power Supply Input (2.5V supply, PLL) Negative Power Supply Input (2.5V supply, PLL) Current Reference Resistor SDI Bias Supply Resistor Negative Power Supply Input (3.3V supply, Serial Input) Serial Data Complement Input Serial Data True Input Positive Power Supply Input (3.3V supply, Serial Input) Negative Power Supply Input (3.3V supply, I/O) Crystal or External 27MHz Clock Input Crystal (Oscillator Output) Positive Power Supply Input (2.5V supply, Digital Logic) ancillary/Control Data Port Function Control Input ancillary/Control Data Port Read/Write Control Input
Name
XTALi/EXT CLK XTALo VDDD ANC/CTRL RD/WR
Note: All LVCMOS inputs have internal pull-down devices except VCLK and ACLK.
Application Information
A typical application circuit for the CLC031A is shown in the Application Circuit diagram. This circuit demonstrates the capabilities of the CLC031A and allows its evaluation in a native configuration. An assembled demonstration board is available, part number SD131EVK. The board may be ordered through any of National's sales offices. Complete circuit board layouts and schematics for the SD131EVK are available on National's WEB site. For latest availability information, please see: www.national.com/appinfo/interface. PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack-up for the CLC031A should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or highlevel inputs and outputs from low-level inputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 F to 0.1 F. Tantalum capacitors may be in the range 2.2 F to 10 F. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the CLC031A as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional VSS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the VSS power supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by prowww.national.com 28
viding short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. In especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the CLC031A's PLL and serial input power pins. The CLC031A was designed for this situation. The I/O, digital section, PLL and serial input power supply feeds are independent (see pinout description table and pinout drawing for details). Supply filtering may take the form of L-section or pi-section, L-C filters in series with these VDD inputs. Such filters are available in a single package from several manufacturers. Device power supplies must be either sequenced as described in Section POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT and ideally should be applied simultaneously as from a common source. MAINTAINING OUTPUT DATA INTEGRITY The way in which the TRS and other video data characters are specified and are therefore output in parallel form can result in the simultaneous switching of many of the CLC031A's CMOS outputs. Such switching can lead to the production of output high level droop or low level ground bounce. Given in the specifications, VOLP is the peak output LOW voltage or ground bounce and VOHV is the lowest output HIGH voltage or output droop that may occur under dynamic simultaneous output switching conditions. VOHV and VOLP are measured with respect to reference ground. Careful attention to PCB layout, power pin connections to the power planes and timing of the output data clocking can reduce these effects. Consideration must also be given to the timing allocated to external circuits which sample the outputs. The effects of simultaneous output switching on output levels may be minimized by adopting good PCB layout and data
CLC031A
Application Information
(Continued)
output timing practices, especially critical at HD data rates. The power pins feeding the I/O should have low inductance connections to the power and ground planes. It is recommended that these connections use at least two vias per power or ground pin. Short interconnecting traces consistent with good layout practices and soldering rules must be used. Sampling or clocking of data by external devices should be so timed as to take maximum advantage of the steady-state portion of the parallel output data interval. The CLC031A is designed so that video data will be stable at the positivegoing transition of VCLK. Data should not be sampled close to the data transition intervals associated with the negativegoing clock edge. The specified propagation delay and clock to data timing parameters must be observed. When data is being sampled from the video data port together with the ANC port and/or I/O port, it is recommended that the sampling clocks be synchronized with the video clock, VCLK, to minimize possible effects from ground bounce or output droop on sampled signal levels. PROCESSING NON-SUPPORTED RASTER FORMATS The number and type of HD raster formats has proliferated since the CLC031A was designed. Though not specifically capable of fully or automatically processing these new formats, the CLC031A may still be capable of deserializing them. The user is encouraged to experiment with processing these formats, keeping in mind that the CLC031A has not been tested to handle formats other than those detailed in Table 4. Therefore, the results from attempts to process non-supported formats is not guaranteed. The following guidelines concerning device setup are provided to aid the user in configuring the CLC031A to attempt limited processing of these other raster formats.
In general, the device is configured to defeat its automatic format detection function and to limit operation to a general HD format. (The user should consult Table 4 for guidance on the format groups similar to the non-supported one to be processed). Since most non-supported formats are in the HD group, the CLC031A should be configured to operate in HD-ONLY mode by setting bit-5 of the FORMAT 0 register (address 0Bh). Also, the device should be further configured by loading the FORMAT SET[4:0] bits of this register with the general HD sub-format code. The complete data word for this general HD sub-format code with HD-ONLY bit set is 33Fh. Since this format differs from those in the table, the EAV/SAV indicators are disabled. Without these indicators, line numbering and CRC processing are disabled and ANC data extraction will not function. Output video chroma and luma data will be word-aligned. Post-processing of the parallel data output from the CLC031A will be needed to implement CRC checking or line number tracking. USING EXTERNAL VCXO FOR VCLK The EXTERNAL VCLK bit of VIDEO CONTROL 0 (register address 55h) is a special application function which enables use of an external VCXO as a substitute for the internally generated VCLK. Additional circuitry is enabled within the CLC031A which provides phase-frequency detection and control voltage output for the VCXO. An external loop filter and voltage amplifier are required to interface the control voltage output to the VCXO frequency control input. When this function is used, the RBB output function is changed from the bias supply output to the control voltage output of the phase-frequency detector. The VCLK output changes function, becoming the input for the VCXO signal. Figure 7 shows an example using dual VCXOs for VCLK to handle both standard and high definition video.
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CLC031A
Application Information
(Continued)
20020114
FIGURE 7. Using Dual VCXOs for VCLK Example The control voltage output from RBB is externally filtered by the loop filter consisting of a 22.1k resistor in series with a 10nF capacitor, combined in parallel with a 100pF capacitor. This gives a loop bandwidth of 1.5kHz. Since the control voltage is limited to around 2.1V, it requires a level shifter to get the entire pull range on the VCXO. National's LMC7101 is recommended with 100k and 182k resistors as shown in Figure 7 to provide a gain of 1.55, sufficient to drive a 3.3V VCXO. Recommended VCXOs from SaRonix (141 Jefferson Drive, Menlo Park, CA 94025, USA) include the ST1308AAB-74.25 for high definition and the ST1307BAB-27.00 for standard definition. Dual VCXOs require some supporting logic to select the appropriate VCXO. This requires the use of Format[4] (SD/HD) and Lock Detect, which are mapped at power-on to I/O Port Bit 3 and I/O Port Bit 4, respectively. These two signals pass through an AND gate (Fairchild Semiconductor's NC7SZ08 or similar). Its output is high when both Lock Detect and Format[4] are high, which indicates a valid high-definition signal is present. The VCXOs are buffered to control the transition times and to allow easy selection. The output of the AND gate is used to control the Output Enable (OE) function of the buffers. The 74.25MHz VCXO is buffered with the NC7SZ126 with the AND gate output connected to the OE pin of the NC7SZ126, and the 27.00MHz VCXO is buffered with the NC7SZ125 with the AND gate output connected to the OE pin of the NC7SZ125. This circuit uses the 27.00MHz VCXO as default and enables the 74.25MHz VCXO when a valid high-definition signal is present. The outputs from the buffers are daisychained together and sent to the CLC031A's VCLK in addition to other devices, such as the CLC030 serializer.
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CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
Physical Dimensions
unless otherwise noted
inches (millimeters)
64-Pin TQPF Order Number CLC031AVEC NS Package Number VEC-64A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2.
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2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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